//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_TIMER_H__
#define __ELASTOS_TIMER_H__

enum {
    PIT_ClockRate               = 3250000,                      // unit: HZ
    PIT_ClockCycle              = (1000000000 / PIT_ClockRate), // unit: NS
};

enum {
    PIT_Irq                     = 26,
};

// Registers' IO address
#define _OSSR   ((ioport_t)0x80a00014)  // OS Timer Status Register
#define _OSCR0  ((ioport_t)0x80a00010)  // OS Timer Count Register 0
#define _OSMR0  ((ioport_t)0x80a00000)  // OS Timer Match Register 0
#define _OIER   ((ioport_t)0x80a0001c)  // OS Timer Interrupt Enable Register

// OS Timer Status Register (OSSR)
#define _M0     __32BIT(0)
#define _M1     __32BIT(1)
#define _M2     __32BIT(2)
#define _M3     __32BIT(3)
#define _M4     __32BIT(4)
#define _M5     __32BIT(5)
#define _M6     __32BIT(6)
#define _M7     __32BIT(7)
#define _M8     __32BIT(8)
#define _M9     __32BIT(9)
#define _M10    __32BIT(10)
#define _M11    __32BIT(11)

// OS Timer Interrupt Enable Register (OIER)
#define _E0     __32BIT(0)
#define _E1     __32BIT(1)
#define _E2     __32BIT(2)
#define _E3     __32BIT(3)
#define _E4     __32BIT(4)
#define _E5     __32BIT(5)
#define _E6     __32BIT(6)
#define _E7     __32BIT(7)
#define _E8     __32BIT(8)
#define _E9     __32BIT(9)
#define _E10    __32BIT(10)
#define _E11    __32BIT(11)

INLINE void EndOfPITInterrupt()
{
    Outl(_OSSR, _M0);
}

#endif // __ELASTOS_TIMER_H__
